NthOne

A combinational nth set-bit selector with LSB-first priority, found, onehot and index outputs.

NthOne locates the nth set bit in an input vector and outputs a match flag, the bit index and a one-hot mask. Its features include:
+ A tree structure to shorten combinational logic paths.
+ Configurable input vector width and set-bit rank.
+ Generated plain Verilog RTL without vendor IP or device primitives.

0.0.1

0.0.1: First version.

Input vector width (inputWidth): Width of input and onehot output; must be greater than 2 and at most 32 bits. type: IntRange default: 8 min: 3 max: 32
Set-bit rank (zero-based) (n): Find set bit n from LSB to MSB; require 0≤n<ceil(inputWidth/2). Fixed at generation time. type: IntRange default: 0 min: 0 max: 15